Making good electrical contact between surfaces that are not permanently bonded may present challenges. As an example, in the semiconductor processing industry, contacts may need to be applied to the silicon wafers for grounding the wafers during the implantation process, for removing beam induced charge during implantation and/or for controlling the potential of the wafer during the implantation process. Similar situations may exist in other industries, e.g., in the design of switches, relays, plugs and sockets. Typical solutions can involve mechanical deformations, e.g., wiping, piercing, scouring and/or polishing, in order to provide clean conductor-to-conductor junctions. Sometimes liquids, gels and/or pastes may be used to enhance the conductance of the contact. As an example, electrode gels may be employed for enhancing contact with EEG (electro-encephalo-graph) and EKG (electro-cardio-graph) electrodes.
In the semiconductor industry, pointed ground pins may be used to contact the wafers. The points can induce surface finish damage and can contribute to backside contamination through the introduction of foreign particles. Also, the impedance of the resulting contacts may not be as low as may be desirable for some applications, such as such as high beam current implantations, pulsed plasma deposition processes or other processes during which maintaining close control of the potential of the wafer may be critical, even as large and/or rapidly changing currents may need to be transferred. These standard approaches to making low-impedance electrical contact to materials can involve methods that may be undesirable or unacceptable for semiconductor processing, such as the use of large contact forces and the use of liquid, paste or gelled electronic or electrolytic conducting materials to improve contact. Also, the use of sharply pointed contact probes may involve at least local damage at the point of contact and the so-called “spreading resistance” can limit the conductance of the contact.
While Ohmic electronic conduction is highly linear, making electrical contact can often involve highly non-linear processes due to surface insulating and semi-insulating layers and the difficulty in establishing a direct metallurgical bond between two conductors that may be brought transiently into contact. For devices such as relays, when mercury-wetted contacts cannot be used, a “wiping” action at the contact points may be useful. Similarly, circuit board sockets can be distinguished by the nature of the contacts made during device insertion, and whether significant “wiping” action may be achieved during insertion. A “wiping” contact may be useful for electrical contacts between two metals as most metals exhibit some degree of ductility, while their surface insulating layers, typically oxides, hydroxides, sulfides and the like, can commonly be of low intrinsic strength and can be easily perturbed, though aluminum oxide layers may be the common exception.
Continuing with reference to the semiconductor industry, it can be known that implantation methods may require adequate electrical or grounding contacts to the wafer. For example, adequate electrical contact may become more central to the implantation process when the pulsed plasma deposition method, referred to as P2LAD, may be used, as the wafer potential can be pulsed to effect the deposition. For P2LAD, improved electrical contact can aid in improving dosimetry of implant. To ensure proper implantation and adequate electrical contact, it may be desirable to improve contact conductance, i.e., lower impedance, reduce or eliminate wafer surface finish damage created by the electrical contacting means and reduce backside particles generated by the grounding means.
However, improvements to electrical contacting or grounding contacts may be subject to various constraints and issues. Typical silicon wafers can have backside oxide layers that may be natural oxide, or sometimes the backside layers may be intentionally grown. In addition, some silicon wafers may have intentionally created insulating layers on the wafer backside, such as silicon oxides, silicon nitrides or exogenous added material layers. Silicon oxides, as well as others of the backside and insulating layers, can typically be hard, adherent and highly insulating, in contrast to the surface oxide layers on many metals. Material compatibility may be a concern in that grounding structures may be a source of material contamination. For P2LAD, it additionally may be desirable to have not merely a low resistance, but also a low impedance (i.e., low inductance as well as low resistance) contact capable of sinking the pulse-deposition currents without significant shift in wafer potential.